The present invention relates to a manufacturing method of a semiconductor device and, in particular, relates to a doping method of an impurity atom to a horizontal surface and vertical side walls of a cubic three-dimension device.
As an example of a cubic three-dimension device related to the present invention, a Fin (fin) type FET (Field Effect Transistor) will be described with reference to FIG. 2.
A silicon Fin part 11 of a Fin type is formed onto a silicon substrate 1. The silicon Fin part 11 is formed with a drain part D and a source part S, and a channel part is formed between the drain part D and the source part S. A gate electrode G made of polysilicon or a metal is formed through a gate insulation film 9 so as to cover the surface of the channel part between the drain part D and the source part S. In order to reduce an electric resistance, an impurity of high concentration more than 1020 cm−3 is implanted into the drain part D and the source part S. 16 is an insulation layer.
As a method for performing doping (implanting) to vertical side walls of the drain part and the source part of a three-dimension Fin type FET, the present inventors have proposed a method shown in FIGS. 3A to 3D (however, it is still unpublished). FIGS. 3A to 3D illustrate an area shown by a dashed line in FIG. 2 with a sectional view.
In FIG. 3A, a silicon Fin part 11 is formed onto a silicon substrate 1 with an etching process by using a hard mask 12 such as SiO2, SiN or the like. Next, a plane part (a plane part except for the silicon Fin part 11) of the silicon substrate 1 is covered with the insulation layer 16 made of SiO2 or the like and a deposited film 2 including Boron B is formed with plasma to both side walls of the silicon Fin part 11 in the state where the hard mask 12 used in the etching process is remained at an upper end of the silicon Fin part 11. In this process, although the deposited film 2 is formed onto the insulation layer 16 that is the insulation film, the deposited film 2 formed onto the insulation layer 16 is removed later.
Next, by obliquely irradiating an ion beam 5 from an upper left direction (diagonal upper direction) of the silicon Fin part 11, a heavy ion such as Ge, Xe or the like is implanted. As result, by a knock on effect (or action) which will be described later, electro-active impurity in silicon, which are present in the deposited film 2 is implanted into a left side wall of the silicon Fin part 11 (FIG. 3A). Subsequently, by obliquely irradiating the ion beam 5 from an upper right direction (diagonal upper direction) of the silicon Fin part 11, a heavy ion such as Ge, Xe or the like is implanted. As a result, electro-active impurity in silicon, which are present in the deposited film 2 is implanted into a right side wall of the silicon Fin part 11 (FIG. 3B). Thus, an impurity diffusion layer 3 is formed in the both side walls of the silicon Fin part 11 (FIG. 3C). Then, the deposited film 2 is removed (FIG. 3D). In the example, an incidence angle (an angle to a vertical line) of the ion beam 5 to the side wall of the silicon Fin part 11 is within 20° and approximately 10° is preferable.
In the Fin type FET manufactured with the above-mentioned method, an upper portion of the silicon Fin part 11 is never utilized as a channel region of a transistor. However, if the upper portion of the silicon Fin part 11 can be utilized as a channel region of a transistor, it is possible to reduce a height of the silicon Fin part 11 and to increase a Fin width (a size of horizontal direction in FIGS. 3A to 3D) of the silicon Fin part 11. This is advantageous in manufacturing the Fin type FET. Further, it can bring an increase in drive current and the characteristic of the transistor can be improved. Such a Fin type FET is called a TriFET. In this case, it is required to implant the impurity into upper side walls of the silicon Fin part 11, that is an upper flat portion of the silicon Fin part 11, in the same concentration level as the side walls lower than the upper flat portion.
However, in the above method proposed by the present inventors, the impurity implantation to the upper flat portion of the silicon Fin part is never considered. For this reason, it is impossible to effectively utilize the upper portion of the silicon Fin part and therefore the Fin type FET has degraded drive current.